1. Field of Invention
The present invention relates to semiconductor devices that retain data through refreshing, methods of the refreshing, memory systems and electronic apparatuses.
2. Description of Related Art
Currently, the use of VSRAMs (Virtually Static RAMs) as semiconductor memories is well known. Memory cells of a VSRAM are similar to those of a DRAM, with the exception that in a VSRAM, column addresses and row addresses do not need multiplexing. Additionally, a user can use a VSRAM without having to consider refreshing (i.e., refreshing transparency).
It is an object of the present invention to provide a semiconductor device that retains data through refreshing, a method of the refreshing, a memory system and an electronic apparatus.
A method for refreshing a semiconductor device in accordance with the present invention pertains to a method for refreshing a semiconductor device having a memory cell array that is divided in a plurality of blocks. The method can include a first step of placing the semiconductor device in an externally accessible first state, a second step of conducting refreshing during the first state for a block among the plurality of blocks other than a block to be externally accessed, a third step of placing the semiconductor device in an externally inaccessible second state, and a fourth step of conducting refreshing during the second state for at least one of the blocks among the plurality of blocks with a time difference provided with respect to refreshing for the remaining blocks.
The semiconductor device in accordance with the present invention can require refreshing in order to retain data. For this reason, power is consumed by refreshing even in the externally accessible second state. In the second state, power is consumed mainly for refreshing, such that the peak current at the refreshing becomes the maximum current. In accordance with the present invention, refreshing for the entire blocks is not simultaneously performed during the second state, but performed with time differences. As a result, the peak current at the refreshing can be lowered.
Accordingly, in accordance with the present invention, a small size battery such as a button battery can be used as a back-up power supply source. In other words, in many situations there exists a demand that data be backed up only with a button battery. However, since the internal resistance of the button battery is large (several kxcexa9), the voltage fall may become large when the peak current is large. As a result, there are occasions that data cannot be retained. In accordance with the present invention, the peak current at refreshing can be lowered, such that a small size battery such as a button battery can therefore be used as a back-up power supply source.
Also, in accordance with the present invention, in the first state, refreshing is conducted for blocks that require to be refreshed are refreshed while a block to be externally accessed is externally accessed. As a result, the semiconductor device can be effectively operated.
It is noted that the first state can be, for example, an operation state. The second state can be, for example, a power-down state, or a standby state and a power-down state.
The number of blocks to be externally accessed may be one or greater. The number of blocks to be externally accessed can be optionally decided at the time of designing a semiconductor device.
Conducting refreshing for a block can mean, for example, to conduct refreshing for memory cells in a certain row in the block. The row may be one row or plural rows. They can be optionally decided when a semiconductor device is designed.
External access can mean, for example, to read data from or write data in a memory cell.
The method for refreshing a semiconductor device in accordance with the present invention can further include that in the fourth step, refreshing of each of the plurality of blocks is conducted with a time difference provided therebetween.
This can mean that when the plurality of blocks includes, for example, four blocks, refreshing is initially conducted for a first block, refreshing is secondly conducted for a second block, refreshing is thirdly conducted for a third block, and refreshing is finally conducted for a fourth block.
When the number of blocks to be simultaneously refreshed increases, the peak current becomes large. In accordance with the present invention, since refreshing of each of the plurality of blocks is conducted with a time difference being provided therebetween, the peak current can be lowered.
The method for refreshing a semiconductor device in accordance with the present invention can further include that the second step and the fourth step include a fifth step of generating a first refresh address signal that is a signal for selecting a first memory cell group to be refreshed that is located in each of the plurality of blocks, and a sixth step of activating a plurality of refresh request signals that are signals for requesting refreshing for each of the plurality of blocks.
It is noted that the first memory cell group to be refreshed can mean, for example, a plurality of memory cells in a row to be refreshed. The number of memory cells in the first memory cell group to be refreshed may be one or a plural.
The method for refreshing a semiconductor device in accordance with the present invention can further include that in the sixth step in the second state, the plurality of refresh request signals are activated with time differences being mutually provided therebetween. In accordance with the present invention, since time differences can be provided between refreshing operations for the plurality of blocks, the peak current can be lowered.
The method for refreshing a semiconductor device in accordance with the present invention can further include that in the sixth step in the second state, the plurality of refresh request signals for refreshing the first memory cell group in each of the blocks are activated in a specified order, and, the method further including, after the sixth step in the second state, a seventh step of generating a second refresh address signal for selecting a second memory cell group to be refreshed that is located in each of the plurality of blocks based on a signal among the plurality of refresh request signals that lastly becomes non-active.
In accordance with the present invention, refreshing for each of the blocks can be securely conducted during the second state. The reasons therefore are described below in greater detail with respect to an embodiment of the present invention.
The method for refreshing a semiconductor device in accordance with the present invention can further include that the method further includes, after the sixth step in the first state, an eighth step of generating a second refresh address signal for selecting a second memory cell group to be refreshed that is located in each of the plurality of blocks based on all of the plurality of refresh request signals that are non-active.
In accordance with the present invention, refreshing for each of the blocks can be securely conducted during the first state. The reasons therefor are described below in greater detail with respect to an embodiment of the present invention.
The method for refreshing a semiconductor device in accordance with the present invention can be made as follows. The semiconductor device can include a VSRAM (Virtually Static RAM).
In a method for refreshing a semiconductor device, the number of memory cells to be refreshed at once is fewer in an externally inaccessible second state of the semiconductor device than in an externally accessible first state of the semiconductor device. In accordance with the present invention, the peak current can be lowered in the second state.
The method for refreshing a semiconductor device in accordance with the present invention can be made as follows. The semiconductor device can be equipped with a memory cell array including the memory cells, and the memory cell array can be divided into a plurality of blocks.
The method for refreshing a semiconductor device in accordance with the present invention can be made as follows. In the second state, a refreshing operation for each of the memory cells in each of the plurality of blocks is conducted with a time difference provided therebetween.
A semiconductor device in accordance with the present invention pertains to a semiconductor device that retains data through refreshing. The device can include a memory cell array that is divided into a plurality of blocks, and a refresh control circuit that conducts refreshing, during an externally accessible first state of the semiconductor device, for a block among the plurality of blocks other than a block to be externally accessed, and conducts refreshing, during an externally inaccessible second state, for each of the blocks among the plurality of blocks with a time difference provided with respect to one another.
The semiconductor device in accordance with the present invention can be made as follows. The refresh control circuit can include a refresh address signal generation circuit that generates a first refresh address signal that is a signal for selecting a first memory cell group to be refreshed that is located in each of the plurality of blocks, a refresh timing signal control that controls a plurality of refresh timing signals respectively corresponding to the plurality of blocks, and a plurality of refresh request signal generation circuits provided for the corresponding respective plurality of blocks, wherein each of the refresh request signal generation circuits generates a refresh request signal for each of the plurality of blocks based on a corresponding one of the plurality of refresh timing signals.
The refresh address signal generation circuit can include, for example, a RF (refresh) counter.
The semiconductor device in accordance with the present invention can be made as follows. The refresh timing signal control activates the plurality of refresh timing signals with time differences provides therebetween in the second state.
In accordance with the present invention, the plurality of refresh timing signals are activated with time differences provided therebetween. As a result, time differences can be provided between refreshing operations for the plurality of blocks, such that the peak current can be lowered.
The semiconductor device in accordance with the present invention can be made as follows. The refresh timing signal control includes a detection circuit that detects a start of the second state, wherein the refresh timing signal control activates, in the second state, the plurality of refresh timing signals in a specified order based on a detection signal from the detection circuit, and the refresh address signal generation circuit generates, in the second state, a second refresh address signal for selecting a second memory cell group to be refreshed that is located in each of the plurality of blocks based on a signal among the plurality of refresh request signals that lastly becomes non-active.
The semiconductor device in accordance with the present invention can be made as follows. The refresh address signal generation circuit generates, in the first state, a second refresh address signal for selecting a second memory cell group to be refreshed that is located in each of the plurality of blocks based on all of the plurality of refresh request signals that are non-active.
The semiconductor device in accordance with the present invention can be made as follows. The semiconductor device includes a VSRAM (Virtually Static RAM).
Additionally, the above-described semiconductor device can be included in an electronic device in accordance with the present invention.